Fix TNEW in x64 interpreter. Do not force a full GC (ouch).
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@@ -3901,39 +3901,32 @@ static void build_ins(BuildCtx *ctx, BCOp op, int defop, int cmov, int sse)
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case BC_TNEW:
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| ins_AD // RA = dst, RD = hbits|asize
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|.if X64
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| mov L:CARG1d, SAVE_L
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| mov L:CARG1d->base, BASE // Caveat: CARG2d/CARG3d may be BASE.
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| mov L:RB, SAVE_L
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| mov L:RB->base, BASE
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| mov RA, [DISPATCH+DISPATCH_GL(gc.total)]
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| cmp RA, [DISPATCH+DISPATCH_GL(gc.threshold)]
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| mov SAVE_PC, PC
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| jae >5
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|1:
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|.if X64
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| mov CARG3d, RD
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| and RD, 0x7ff
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| shr CARG3d, 11
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| cmp RD, 0x7ff
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| je >3
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|2:
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| mov CARG2d, RD
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| mov RD, [DISPATCH+DISPATCH_GL(gc.total)]
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| mov L:RB, L:CARG1d
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| cmp RD, [DISPATCH+DISPATCH_GL(gc.threshold)]
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| mov SAVE_PC, PC
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| jae >5
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|.else
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| mov RB, RD
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| mov RA, RD
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| and RD, 0x7ff
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| shr RB, 11
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| shr RA, 11
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| mov ARG3, RA
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|.endif
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| cmp RD, 0x7ff
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| je >3
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|2:
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| mov ARG3, RB
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| mov L:RB, SAVE_L
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| mov ARG2, RD
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| mov SAVE_PC, PC
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| mov RD, [DISPATCH+DISPATCH_GL(gc.total)]
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|.if X64
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| mov L:CARG1d, L:RB
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| mov CARG2d, RD
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|.else
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| mov ARG1, L:RB
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| cmp RD, [DISPATCH+DISPATCH_GL(gc.threshold)]
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| mov L:RB->base, BASE
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| jae >5
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|1:
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| mov ARG2, RD
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|.endif
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| call extern lj_tab_new // (lua_State *L, int32_t asize, uint32_t hbits)
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| // Table * returned in eax (RC).
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@@ -3946,16 +3939,10 @@ static void build_ins(BuildCtx *ctx, BCOp op, int defop, int cmov, int sse)
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| mov RD, 0x801
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| jmp <2
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|5:
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|.if X64
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| call extern lj_gc_step_fixtop@4 // (lua_State *L)
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| movzx RD, PC_RD
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| mov L:CARG1d, L:RB
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| jmp <1
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|.else
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| mov L:FCARG1, L:RB
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| call extern lj_gc_step_fixtop@4 // (lua_State *L)
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| movzx RD, PC_RD
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| jmp <1
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|.endif
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break;
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case BC_TDUP:
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| ins_AND // RA = dst, RD = table const (~) (holding template table)
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